1. Field of the Invention
The present invention relates generally to discrete-time input circuits, and more specifically, to a discrete-time analog-to-digital converter (ADC) input circuit having input signal and common-mode current nulling.
2. Background of the Invention
Measurement input circuits for ADCs must typically handle large common mode voltage differences between the input signal and the feedback reference voltage, especially in applications such as AC line power or DC measurement circuits and in test equipment such as digital voltmeters (DVMs). Even with the use of transformers or resistive dividers, the dynamic range needed for universal applicability typically requires one or more programmable gain stages to preserve signal to noise ratio (SNR) and a high input impedance buffer stage at the input to avoid loading the measured source, in particular where the source may have a large input voltage range requiring several gain settings in the first stage of the ADC analog section.
Discrete-time sampling circuits, such as those utilized in switched-capacitor based delta-sigma modulator ADCs have been used in such measurement circuits, but input buffer circuits are still typically required, since the input sampling capacitor must typically be made large enough to reduce the magnitude of thermal noise introduced in the input of the first amplifier/integrator stage. Furthermore, in programmable gain applications, the input sampling capacitor is typically adjusted, since adjusting the feedback capacitor of the integrator would impose variable performance requirements on the amplifier that is used in the integrator.
Raising the input capacitance of the input sampling capacitor to the level required to maintain low thermal noise injection lowers the impedance of the input circuit, and thus the above-mentioned buffers are typically required in such sampling circuits. The buffer must be designed to handle the relatively large differences that are typical between the common-mode voltage of the input source and the common-mode reference voltage of the input stage. In some implementations, a common-mode voltage reference is supplied to cancel the common-mode voltage of the measurement source thereby simplifying the requirements for the buffer circuit, but such implementations typically require an external integrated circuit terminal, and buffering for the common-mode voltage source. Furthermore, the buffer circuits typically require considerable additional operating power.
Therefore, it would be desirable to provide a low-power high-impedance discrete-time input circuit for an ADC that does not require buffering or external common-mode reference.